SONOS (silicon-oxide-nitride-oxide-silicon) is a nonvolatile, trapped-charge semiconductor memory technology that provides several advantages over conventional floating-gate flash memories, including immunity from single point failures and programming at lower voltages. In contrast to floating-gate devices, which store charge on a conductive gate, SONOS devices trap charge in a dielectric layer. SONOS transistors are programmed and erased using a quantum mechanical effect known as uniform channel, modified Fowler-Nordheim tunneling. This method of programming and erase is known in the industry to provide better reliability than other methods such as hot carrier injection. A SONOS transistor is an insulated-gate field effect transistor (IGFET) with a charge-trapping dielectric stack between a conventional control gate and a channel in the body or substrate of the transistor. A SONOS transistor can be fabricated as a P-type or N-type IGFET using CMOS (complementary metal-oxide-semiconductor) fabrications methods.
A SONOS transistor is programmed or erased by applying a voltage of the proper polarity, magnitude and duration between the control gate and the substrate. A positive gate-to-substrate voltage causes electrons to tunnel from the channel to a charge-trapping dielectric layer and a negative gate-to-channel voltage causes holes to tunnel from the channel to the charge-trapping dielectric layer. In one case, the threshold voltage of the transistor is raised and in the other case, the threshold voltage of the transistor is lowered. The threshold voltage is the gate-to-source voltage that causes the transistor to conduct current when a voltage is applied between the drain and source terminals. For a given amount of trapped charge, the direction of the threshold voltage change depends on whether the transistor is an N-type or P-type FET.
FIG. 1A illustrates the change in threshold voltage VT of an N-type SONOS transistor as a function of time for a programming voltage of +10 volts and an erase voltage of −10 volts. After approximately 10 milliseconds, the programmed threshold voltage is greater than +1 volt and the erased threshold is less than −1 volt. After a programming or erase operation is completed, the state of the transistor can be read by setting the gate-to-source voltage to zero, applying a small voltage between the drain and source terminals and sensing the current that flows through the transistor. In the programmed state, the N-type SONOS transistor will be OFF because the gate-to-source voltage will be below the programmed threshold voltage VTP. In the erased state, the N-type SONOS transistor will be ON because the gate-to-source voltage will be above the erased threshold voltage VTE. Conventionally, the ON state is associated with a logical “0” and the OFF state is associated with a logical “1.”
FIG. 1B illustrates a small segment of a conventional array of one transistor (1T) N-type SONOS memory cells 100 containing four memory cells (A, B, C, D) in two rows (Row 0, Row 1) and two columns (Col 0, Col 1).
Each row includes a word line (WL0, WL1) that is used to select or deselect the row. All the cells share a common substrate voltage (SUB). Each column includes a source line (SL0, SL1) connected to the source terminals of all the transistors in that column, and a bit line (BL0, BL1) connected to the drain terminals of all the transistors in the column. Like other types of non-volatile memory, write operations in SONOS memories are performed on a row by row basis.
A write operation consists of a bulk erase operation on a row, followed by program or inhibit operations on individual cells in the row. Memory transistors that are to be written to a “1” (programmed) state are exposed to the full programming voltage (e.g., 10 volts). Memory transistors that are to be “written” to a “0” state are inhibited from programming because the previous bulk erase operation has already placed them in the “0” state. The inhibit function is accomplished applying an inhibit voltage to those memory transistors in the row that are to remain in the “0” or erased state, that lowers the total voltage across the transistor.
FIG. 1B illustrates a bulk erase operation on Row 0. As illustrated in FIG. 1B, the voltages are selected to impress −10 volts between the gates of transistors A and B and their respective source and substrate terminals. In Row 1, however, the word line (WL1) voltage is selected so that the gate-to-source and gate-to-substrate voltages on transistors C and D are all zero, so the states of transistors C and D are unchanged. In particular, transistor D, in a programmed state (shown schematically as a shaded trapping region to represent stored electrons), remains programmed and transistor C, in an erased state, remains erased.
FIG. 1C illustrates the second step in a conventional write operation on Row 0, where transistor A is being programmed (written to a “1”) and transistor B is being inhibited from programming (written to a “0”). In this step, the word line voltages and common substrate voltages in both rows are reversed, and the bit line voltage on column 0 (BL0) is also reversed, but an intermediate voltage (+2 volts) is applied to the bit line of column 1 (BL1). When the word line (WL0) voltage of +6V is applied transistor B, it is turned on, and the +2V from the bit line (BL1) is transferred to its channel. This voltage reduces the gate-to-drain and channel voltage on transistor B (to +4 volts) reducing the programming field so that the threshold shift (VTE) of SONOS transistor B is small. The tunneling that does occur is known as “inhibit disturb” or soft-programming and causes a small increase in threshold voltage (around +200 mV) during the inhibit write operation.
In Row 1, the voltages on transistor C are all the same, so transistor C is unaffected by the write operation on Row 0. However, transistor D is affected (assumed to be programmed with trapped electrons in the memory layer). As a result of the inhibit voltage on BL1, the gate-to-drain voltage on transistor C is −6 volts. This voltage condition, which can erase the programmed SONOS transistor over long periods of disturb, causes hole tunneling from the drain, source, and channel to the memory layer. The tunneling that occurs is known as “bit line disturb” or soft erase and causes a small decrease in the threshold voltage of the programmed cell each time a cell in Column 1 in any other row is inhibited during a write operation on that row. However over many bit line disturb cycles, the threshold shift may cause cell read failures.
The maximum number of consecutive inhibit disturbs on an erased cell is limited to one (1) because the cell is always erased during the first part of a write operation. In contrast, the maximum number of consecutive bit line disturbs on a programmed cell in a given row and column is the total number of write operations on all other rows where an inhibit voltage is applied to the bit line on the given column. For example, if there are 64 rows in an array, and each row is written to (cycled) 100,000 times, then the maximum number of bit line disturbs that can be seen by the programmed cell is 64 minus 1 times 100,000, which equals 6,300,000 bit line disturbs. This means, statistically, that shifts in programmed threshold voltages are the limiting factor in conventional SONOS memories. The reliability of non-volatile memories is measured by their endurance (number of write cycles) and data retention. FIG. 1D is a graph comparing the data retention of an undisturbed SONOS cell and a programmed SONOS cell after 1,000,000 bit line disturbs as described above.
In FIG. 1D, the undisturbed SONOS cell exhibits a large initial separation at its beginning of life (BOL) between its programmed and erased threshold voltages. Over time, charge leakage causes the programmed threshold voltage to decrease and the erased threshold voltage to increase. A sense widow for reading the cell (defined as the minimum threshold voltage that reliably represents a “1” and the maximum threshold voltage that reliable represents a “0”) is positioned to maximize the time to the end of life (EOL) of the cell (so that on average, the programmed threshold voltage and erased threshold voltage decay to their respective sense window limits at the same time. In the case of the disturbed cell, however, the BOL value of the programmed threshold voltage is reduced by the cumulative effect of soft erase during cycling, and the rate of decay is increased because each bit line disturb may cause some damage to the tunneling layer that increases the charge leakage rate.